Voltage controlled oscillator

ABSTRACT

A voltage-controlled oscillator comprising a LC tank circuit coupled to a pair of transistors and crossed-coupled to a pair of emitter follower transistors each transistor having a collector, an emitter and a base, the voltage controlled oscillator being characterized in that a supply voltage applied to the collectors of the emitter follower transistors is substantially different from a supply voltage applied to the bases of the emitter follower transistors.

The invention relates to a voltage-controlled oscillator comprising a LCtank circuit coupled to a pair of transistors and crossed-coupled to apair of emitter follower transistors, each transistor having acollector, an emitter and a base.

The invention also relates to a pseudo random generator comprising sucha voltage-controlled oscillator.

Voltage controlled oscillators (VCOs) are extensively used incommunication systems as receivers, transmitters, and transceivers. Theyalso could be used as clock generators for digital systems. A classicalprior-art differential LC VCO is shown in FIG. 4. It comprises a pair oftransistors Tp1, Tp2 having their emitters coupled to a current sourceIe for biasing. A LC tank circuit comprises inductors Lp1 and Lp2coupled to a pair of voltage controlled capacitors implemented withvariable capacitance diodes D1 and D2. A voltage VT controls thecapacitance of the diodes D1 and D2. The pair of transistors Tp1, Tp2 iscross-coupled i.e. a collector of one of the transistors is connected toa base of the other transistor and reciprocally. A major disadvantage ofthe topology shown in FIG. 4 is that the two transistors operate insaturation due to the relatively same DC bias at base and collector. Thebase-collector diodes are forward-biased by the voltage swing, limitingthe maximum attainable swing.

U.S. Pat. No. 5,847,621 discloses an LC oscillator with delay tuningcomprising a pair of transistors coupled to an LC tank circuit. Across-coupling feedback is realized with a pair of emitter followers.The emitter followers and the pair of transistors are biased via currentgenerators controlled by a bias voltage. Using voltage followers theoscillator is better buffered when it is coupled to a load impedance. Itis observed that the bias voltage for the emitter followers base andcollector are substantially the same and the transistors also work atsaturation. Hence, as it was previously shown, a maximum voltage swingcannot be obtained. Furthermore, the swing limitation determines ahigher phase noise.

U.S. Pat. No. 6,150,893 discloses a voltage-controlled oscillatorcomprising two sub-circuits, each sub-circuit comprising a pair oftransistors. The first sub-circuit is an LC oscillation sub-circuit inwhich each transistor has a capacitive transformer in it's feedbackloop. It is observed that the transistors in the two sub-circuits havedifferent bias voltages at their bases and at their collectors but theadditional capacitors require an additional chip area.

It is therefore an object of the present invention to obtain avoltage-controlled oscillator having an improved output voltage swingand a lower phase noise.

In accordance with the invention this is achieved in avoltage-controlled oscillator as described in the introductoryparagraph, the voltage-controlled oscillator being characterized in thata supply voltage applied to the collectors of the emitter followertransistors is substantially different from a supply voltage applied tothe bases of the emitter follower transistors. When NPN bipolartransistors are considered, the bias voltage of the collectors is higherthan the bias voltage of the bases of the transistors. The complementarysituation occurs when PNP bipolar transistors are considered. Thetransistors could be implemented in different technologies as Si, Si—Geand so on. Because the transistors do not operate in saturation mode theoutput voltage swing is increased.

In an embodiment of the invention the LC tank circuit is coupled to thesupply voltage via a bipolar transistor connected as a diode forgenerating substantially different supply voltages for the bases andcollectors of the emitter follower transistors. Different biases for thebases and collectors of the transistors could be obtain using e.g.resistors and decupling capacitors. But the area occupied by the circuitincreases especially due to the capacitors. Hence, using a bipolartransistor connected as diode results in a more efficient use of thesemiconductor area where the oscillator is implemented.

Another aspect of the invention provides a pseudo random sequencegenerator comprising a first sequence generator and a second sequencegenerator driven by the voltage controlled oscillator. A first output ofthe first sequence generator and a second output of the second sequencegenerator are coupled to a multiplexer. The multiplexer is driven by anoutput signal of the voltage controlled oscillator for selecting eithera signal outputted by the first sequence generator or a signal outputtedby the second sequence generator. The multiplexer generates at a thirdoutput a binary signal having a bit-rate that is substantially double abit-rate obtained either at the first output or at the second output.Pseudo random sequence generators are extensively used in testingdigital integrated circuits to generate test vectors. It is preferablythat the test of a circuit to last as short time as possible. The testspeed is determined inter alia by a period of the voltage-controlledoscillator output signal that is used as clock. An ordinary sequencegenerator generates a new test vector whenever occurs a transition frome.g. a low level to a high level in the amplitude of the clock signal.Otherwise said, the speed of generation of test vectors has the samefrequency as the frequency of the clock. A substantially double speedfor generating the test vectors is obtained using two interleavedsequence generators coupled to a multiplexer. The first sequencegenerator generates an output signal at a transition from a low level toa high level in the amplitude of the clock signal, the second sequencegenerator generating an output signal at a high level to a low level inthe amplitude of the clock signal.

In an embodiment of the invention each of the sequence generators,comprises a closed-chain of flip-flops each having a data input, a clockinput, a preset input and an output. The pseudo random sequencegenerator further comprises a feedback including a XOR gate having anoutput coupled to a first of the flip-flops data input and a pair ofinputs coupled to a pair of outputs of the flip-flops. The feedback isused for allowing the register to work properly in a ring mode. Theoutput of the pseudo random generator is obtained at the outputs of theflip-flops as a vector of binary signals.

The above and other features and advantages of the invention will beapparent from the following description of exemplary embodiments of theinvention with reference to the accompanying drawings, in which:

FIG. 1 depicts a voltage-controlled oscillator according to theinvention,

FIG. 2 depicts a pseudo random sequence generator according to anembodiment of the invention,

FIG. 3 depicts a chain of flip-flops used in the random generatoraccording to an embodiment of the invention, and

FIG. 4 depicts a prior-art voltage controlled oscillator.

FIG. 1 depicts a voltage-controlled oscillator according to theinvention. The voltage-controlled oscillator comprises a LC tank circuitL1, L2, VD1, VD2 coupled to a pair of transistors T2, T3 andcrossed-coupled to a pair of emitter follower transistors T0, T4. Eachof the transistors has a collector, an emitter and a base. A supplyvoltage applied to the collectors of the emitter follower transistorsT0, T4 is substantially different than a supply voltage applied to thebases of the emitter follower transistors T0, T4. The inductance of theinductors L1, L2 and the capacitance of the capacitors VD1, VD2,determine an oscillation frequency of the voltage-controlled oscillator.The capacitors VD1 and VD2 are varicap diodes. Hence, they arecontrollable by a tuning voltage Vt. Capacitors C having a capacitancesubstantially larger that the maximum capacity of the varicap diodes areused as decupling capacitors having a relatively small influence on theoscillation frequency of the voltage-controlled oscillator. Resistors Rare used for biasing the varicap diodes. The collectors of thetransistors T2 and T3 are cross-coupled to the bases of the transistorsT4 and T0, respectively. The transistors T4 and T0 are connected asemitter followers being biased via current generators T1 and T5, thecurrent generators being controlled by a bias voltage V_(B). It isobserved that the collectors of the transistors T0 and T4 are connectedto the supply voltage Vcc and their bases are connected to asubstantially lower voltage that could be approximated as Vcc-V_(BE),where V_(BE) is a base to emitter voltage of a bipolar transistor T7. Itshould be pointed out here that a resistance of the inductors L1, L2 isnegligible because the inductance should have a quality factor as higheras possible reducing the losses in the tank circuit. When Vcc was 3V theoutput oscillation voltage was 1.2 V while the output swing of theprior-art voltage-controlled oscillator shown in FIG. 4 is approximately0.5V. The corresponded phase noise of the voltage-controlled oscillatorshown in FIG. 1 is circa −108 dBc/Hz while the phase margin of theprior-art oscillator is −95 dBc/Hz. It is further observed that theemitter follower transistors buffer the voltage-controlled oscillatorfor minimizing the influences of a load on the amplitude and frequencyof the signal generated by the oscillator. The circuit shown in FIG. 1was implemented using NPN bipolar transistors but a skilled person inthe art could relatively easy implement the circuit using PNP bipolartransistors. Furthermore, the transistors could be implemented indifferent technologies as Si, Si—Ge and so on. Because the transistorsdo not operate in saturation mode the output voltage swing is increased.It is also observed that different biases for the bases and collectorsof the transistors could be obtain using e.g. resistors and relativelyhigh capacitance decoupling capacitors. But the area occupied by thecircuit increases especially due to the capacitors. Hence, using abipolar transistor connected as diode results in a more efficient use ofthe semiconductor area where the oscillator is implemented.

FIG. 2 depicts a pseudo random sequence generator (PRSG). The PRSGcomprises a first sequence generator R1 and a second sequence generatorR2 driven by a voltage controlled oscillator as shown in FIG. 1. A firstoutput O1 of the first sequence generator R1 and a second output O2 ofthe second sequence generator R2 are coupled to a multiplexer M drivenby an output signal I of the voltage controlled oscillator. The signal Iselects either a signal outputted by the first sequence generator R1 ora signal outputted by the second sequence generator R2. The multiplexerM generates at a third output O3 a binary signal having a bit-ratesubstantially double the bit rate obtainable with only one of thesequence generators R1, R2. A sequence is defined hereinafter as asuccession of binary data (bits). The first sequence generator generatesan output bit at the first output O1 only at a transition from a lowvalue to a high value of the signal I. Hence, in every period of thesignal I a bit is generated at the first output O1. Similarly, a bit isgenerated at the second output O2 at every transition from a high levelto a low level of the signal I. The multiplexer M transfer the signalfrom it's input I1 to it's output O3 when the signal I has a high leveland the signal from it's input I2 to the output O3 when the signal I hasa low level. Following a transition from a low value to a high value ofthe signal I the bit presented at the first input I1 is transferred tothe output O3. After a transition from a high level to a low level ofsignal I the signal from the input I2 is transferred to the output O3.Hence, every half period of the signal I a bit is generated at theoutput O3. If we note as BR the bit rate either at the output O1 or atthe output O2 then the bit rate at the output O3 noted as 2BR issubstantially 2*BR. This feature is very attractive because the bit rateat the output O3 is obtained using a relatively low frequency clocksignal I.

FIG. 3 depicts a chain of flip-flops FF1, . . . , FF_(n), used in thepseudo random generator according to an embodiment of the invention. Thechain of flip-flops represents a presetable shift register connected ina ring for generating a pseudo-random vector of digital signals. Theoutput signal I of the voltage-controlled oscillator shown in FIG. 1drives the pseudo random sequence generator. The pseudo random generatorcomprises a chain of N flip-flops each having a data input D₁, . . . ,D_(n-1), D_(n), a clock input C₁, . . . , C_(n-1), C_(n), a preset inputP₁, . . . , P_(n-1), P_(n) and an output Q₁, . . . , Q_(n-1), Q_(n). Forsimplicity we consider that the flip-flop FF₁ is the first one in thechain and the flip-flop FF₁ is the last one in the chain. The pseudorandom sequence generator further comprises a feedback including a XORgate having an output coupled to the first of the flip-flops FF₁ datainput D₁ and a pair of inputs coupled to a pair of outputs Q_(n),Q_(n-1) of the last and one-before-last flip-flops. The flip-flops arefirst preset in a binary state using binary signals inputted via presetinputs P₁, . . . , P_(n-1), P_(n). Hence, the binary values P_(i) ispresent at the output Q_(i). Every positive edge of the signal Idetermines a transfer of the binary value from an output Q_(i) to theoutput Q_(i+1). In order to close the chain, a feedback comprising a XORgate between the outputs Q_(n-1) and Q_(n) is provided.

It is observed that the signal I could be single ended i.e. either In orIp in FIG. 1 or differential. Accordingly the flip-flops could be singleended or differential.

It is remarked that the scope of protection of the invention is notrestricted to the embodiments described herein. Neither is the scope ofprotection of the invention restricted by the reference numerals in theclaims. The word ‘comprising’ does not exclude other parts than thosementioned in the claims. The word ‘a(n)’ preceding an element does notexclude a plurality of those elements. Means forming part of theinvention may both be implemented in the form of dedicated hardware orin the form of a programmed purpose processor. The invention resides ineach new feature or combination of features.

1. A voltage-controlled oscillator comprising a LC tank circuit coupled to a pair of transistors and crossed-coupled to a pair of emitter follower transistors, each transistor having a collector, an emitter and a base, the voltage controlled oscillator being characterized in that a supply voltage applied to the collectors of the emitter follower transistors is substantially different from a simply voltage applied to the bases of the emitter follower transistors, and wherein the LC tank circuit is coupled to the supply voltage via a bipolar transistor connected as a diode for obtaining a substantially different supply voltages for the bases and collectors of the emitter follower transistors.
 2. A pseudo random sequence generator comprising a first sequence generator and a second sequence generator driven by a voltage controlled oscillator as claimed in claim 1, a first output of the first sequence generator and a second output of the second sequence generator being coupled to a multiplexer driven by an output signal of the voltage controlled oscillator for selecting either a signal outputted by the first sequence generator or a signal outputted by the second sequence generator, the multiplexer generating at a third output a binary signal having a bit-rate that is substantially double a bit-rate obtained either at the first output or at the second output.
 3. A pseudo random sequence generator as claimed in claim 2, wherein each of the sequence generators comprises a closed-chain of flip-flops each having a data input, a clock input, a preset input and an output, the pseudo random sequence generator further comprising a feedback including a XOR gate having an output coupled to a first of the flip-flops data input and a pair of inputs coupled to a pair of outputs of the flip-flops. 